FPGA/verilog-ethernet
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218 Commits

Author SHA1 Message Date
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
71235c0b92 64 bit Ethernet FCS checker optimizations 2015-11-03 15:32:23 -08:00
Alex Forencich
17bf03d7a2 10G MAC RX optimizations 2015-11-03 15:30:08 -08:00
Alex Forencich
26aacea6ef Remove unused code 2015-10-28 12:40:23 -07:00
Alex Forencich
73e0a1cff4 Fail outgoing frames on tvalid deassert 2015-10-20 16:05:23 -07:00
Alex Forencich
475f897a31 Unconditional increment length 2015-10-20 16:04:47 -07:00
Alex Forencich
2a59c7db1c Update generate scripts to use argparse 2015-10-19 19:26:59 -07:00
Alex Forencich
9d90f09de5 Rework CRC check 2015-10-09 22:56:52 -07:00
Alex Forencich
08afe3a5d2 Synchronize MAC status signals 2015-10-09 22:51:55 -07:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
55071645fd Update async FIFO instances 2015-10-09 22:35:25 -07:00
Alex Forencich
4156d8511a Rework CRC check 2015-08-07 12:13:44 -07:00
Alex Forencich
af8bed8237 Update for compatibility with older versions of Python 2015-07-14 08:29:54 -07:00
Alex Forencich
2667c9c631 Update for compatibility with older version of Python 2015-07-09 11:35:55 -07:00
Alex Forencich
abe0d926ba Consider any control characters in packet body as errors 2015-06-23 08:55:39 -07:00
Alex Forencich
dbf720ffbe Improve 10G PHY TX timing performance 2015-06-23 07:43:06 -07:00
Alex Forencich
0ecd354d7f Fix instance name 2015-06-07 22:07:04 -07:00
Alex Forencich
455ddf5df2 Fix error detect in 10G MAC 2015-06-06 00:49:40 -07:00
Alex Forencich
bfc97ac311 Fix error detect in 1G MAC 2015-06-05 23:42:43 -07:00
Alex Forencich
14a2caa994 Rework 10G ethernet MAC TX to add input register 2015-05-17 01:39:59 -07:00
Alex Forencich
0352d55084 Add default case 2015-05-16 22:34:29 -07:00
Alex Forencich
15edfa0f85 Add missing initialize 2015-05-16 22:32:02 -07:00
Alex Forencich
ec95a6055d Feed through and synchronize FIFO status signals 2015-05-12 19:12:23 -07:00
Alex Forencich
8fea20ef77 Fix frame_ptr_reg width 2015-05-12 16:57:14 -07:00
Alex Forencich
8aa5ec5118 Improve ip_eth_rx_64 module timing performance 2015-05-08 21:06:33 -07:00
Alex Forencich
5ae8eb9611 Improve ip_eth_tx_64 module timing performance 2015-05-08 20:37:31 -07:00
Alex Forencich
16fec34ddc Default FIFO size at least 2 MTU (3000 bytes) 2015-05-08 01:44:55 -07:00
Alex Forencich
00a87b26b3 Add FIFO wrapper for 10G MAC module 2015-05-08 00:07:09 -07:00
Alex Forencich
bf349b16ba Add 10G MAC module 2015-05-08 00:05:21 -07:00
Alex Forencich
73bebaba46 Add FIFO wrapper for gigabit MAC module 2015-05-07 23:45:30 -07:00
Alex Forencich
3a180bd24f Improve error signal handling 2015-05-07 19:08:16 -07:00
Alex Forencich
0be84e3b03 Write to _next instead of _reg in async block 2015-05-04 01:17:39 -07:00
Alex Forencich
71511b3671 Remove unused register 2015-04-20 23:37:57 -07:00
Alex Forencich
db6a6e23f5 Add 64 bit Ethernet FCS checker 2015-03-22 01:05:57 -07:00
Alex Forencich
51b5335318 Remove z from default states for FSM inference 2015-03-09 02:38:39 -07:00
Alex Forencich
d73b296903 Properly handle short packets 2015-03-04 13:06:29 -08:00
Alex Forencich
17ad08e412 Add 64-bit Ethernet FCS inserter 2015-03-04 00:33:26 -08:00
Alex Forencich
263891b3f6 Make sure all paths set state_next 2015-03-04 00:31:41 -08:00
Alex Forencich
23fa1f1207 Handle tlast on first cycle 2015-03-03 21:46:02 -08:00
Alex Forencich
d3e30d0a73 Fix padding bug 2015-02-28 23:09:41 -08:00
Alex Forencich
14e71d568d Improve classifier logic by registering payload select signals 2015-02-28 19:14:22 -08:00
Alex Forencich
d57c857d88 Put PHY interface registers into IOBs for timing 2015-02-28 18:24:20 -08:00
Alex Forencich
7532915bb7 Add GMII PHY interface module 2015-02-28 01:11:03 -08:00
Alex Forencich
6b4dd02946 Resolve multiple driver issue 2015-02-28 00:43:27 -08:00
Alex Forencich
b892fd1172 Add UDP complete module and testbench 2015-02-26 22:57:24 -08:00
Alex Forencich
635f05e9c6 Remove udp_ip_protocol input 2015-02-26 22:37:40 -08:00
Alex Forencich
10108d5d1a Add 2 port IP mux components 2015-02-26 22:05:07 -08:00
Alex Forencich
d34aaf784d Add UDP modules 2015-02-26 21:19:26 -08:00
Alex Forencich
6dee616834 Add gigabit MAC module 2015-02-26 19:16:08 -08:00
Alex Forencich
bfe6c37ca9 Add ethernet FCS inserter and checker 2015-02-26 19:00:33 -08:00