FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-28 07:03:08 +08:00
Code Issues Projects Releases Wiki Activity
966 Commits 1 Branch 0 Tags
Commit Graph

3 Commits

Author SHA1 Message Date
Alex Forencich
32d99b4dd9 Use constants from cocotbext-eth 2021-11-07 18:21:06 -08:00
Alex Forencich
a540e50e1c Fix XGMII to BASE-R control character mapping 2021-10-15 16:14:02 -07:00
Alex Forencich
c0e2eb2b07 Add BASE-R serdes models for cocotb 2021-10-15 00:36:56 -07:00