FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
07b4efa9ba Switch out Xilinx PHY core in ExaNIC X10 example design 2019-01-18 13:49:46 -08:00
Alex Forencich
82454e4ae1 Add ExaNIC X10 example design 2019-01-08 17:22:01 -08:00