FPGA/verilog-ethernet
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14 Commits

Author SHA1 Message Date
Alex Forencich
609aac39a0 Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:47:30 -07:00
Alex Forencich
9b5a8cf24a Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:39:44 -07:00
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
d2fedc4134 Rename ports 2018-11-07 22:35:06 -08:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
9a507b388d Update LFSR module 2017-06-09 21:17:28 -07:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
47ca9a8725 Replace eth_crc modules for generic lfsr module 2016-06-28 17:31:58 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
d73b296903 Properly handle short packets 2015-03-04 13:06:29 -08:00
Alex Forencich
263891b3f6 Make sure all paths set state_next 2015-03-04 00:31:41 -08:00
Alex Forencich
bfe6c37ca9 Add ethernet FCS inserter and checker 2015-02-26 19:00:33 -08:00