FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
1279dcbf47 Back out previous change 2019-07-15 18:09:14 -07:00
Alex Forencich
9d553f2ad4 Also need to use tready 2019-07-15 15:24:12 -07:00
Alex Forencich
d88ada105d Add PTP TS extract module 2019-07-15 15:17:58 -07:00