FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
ac97cffc2b Properly reset all registers 2015-07-13 23:15:09 -07:00
Alex Forencich
dfab866e99 Remove unused reg 2015-07-13 23:09:02 -07:00
Alex Forencich
10fd51f192 Add SRL FIFO module and testbench 2014-12-03 18:49:33 -08:00