FPGA/verilog-ethernet
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14 Commits

Author SHA1 Message Date
Alex Forencich
fb4abb6b39 Fix widths 2019-03-14 14:44:00 -07:00
Alex Forencich
6b1b36ded6 Assert header ready earlier if possible 2018-11-07 23:10:07 -08:00
Alex Forencich
b223c94adb Use registered header 2018-11-07 23:08:40 -08:00
Alex Forencich
d2fedc4134 Rename ports 2018-11-07 22:35:06 -08:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
51b5335318 Remove z from default states for FSM inference 2015-03-09 02:38:39 -07:00
Alex Forencich
f35ecece83 Initialize tkeep properly 2014-11-20 22:52:52 -08:00
Alex Forencich
0f62d31fef Rework ARP datapath modules to separate output register 2014-10-28 01:55:36 -07:00
Alex Forencich
fdb31878e9 Remove length fields from ARP transmit module 2014-09-17 12:36:56 -07:00
Alex Forencich
ea2b1b99d0 Add ARP frame to Ethernet frame modules 2014-09-15 19:06:02 -07:00