FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
14e71d568d Improve classifier logic by registering payload select signals 2015-02-28 19:14:22 -08:00
Alex Forencich
b892fd1172 Add UDP complete module and testbench 2015-02-26 22:57:24 -08:00