FPGA/verilog-ethernet
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5 Commits

Author SHA1 Message Date
Alex Forencich
30a35c3d73 Convert async fifo to common reset 2015-10-08 12:52:51 -07:00
Alex Forencich
516c50d786 Add FIFO reset tests 2015-07-09 11:13:25 -07:00
Alex Forencich
e65173b7ee Add overflow, bad_frame, and good_frame status outputs to frame FIFOs 2015-05-12 17:52:41 -07:00
Alex Forencich
02a7f4d5ed Update testbenches to python 3 2015-03-21 03:32:19 -07:00
Alex Forencich
10e0d7d1bb Add AXI async frame fifo and testbench 2014-11-08 21:29:39 -08:00