FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-02-04 07:13:13 +08:00
Code Issues Projects Releases Wiki Activity
269 Commits 1 Branch 0 Tags
Commit Graph

1 Commits

Author SHA1 Message Date
Alex Forencich
fd1ec1690f Add sync_reset module and timing constraints 2020-03-27 18:04:04 -07:00