FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
88150c9d5f Update and rework endpoints, update testbenches 2016-09-13 15:24:02 -07:00
Alex Forencich
a430e4463e Add RGMII endpoint and PHY interface module 2016-06-29 06:13:46 -07:00