FPGA/verilog-ethernet
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9 Commits

Author SHA1 Message Date
Alex Forencich
3bbf8524d6 Compute DEST_WIDTH 2018-10-24 22:21:31 -07:00
Alex Forencich
fd7f65d5ad Convert generated switch to verilog parametrized switch 2018-10-24 16:12:56 -07:00
Alex Forencich
3063bba54b Update testbenches to use wait 2018-07-02 16:19:35 -07:00
Alex Forencich
c5837daa2f Update testbenches to use instances() 2018-06-13 22:26:10 -07:00
Alex Forencich
5df7efe516 Happy new year 2018-02-26 12:25:20 -08:00
Alex Forencich
de590517a9 Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream switch 2017-11-20 20:17:20 -08:00
Alex Forencich
aebe0549dd Happy new year 2017-05-18 13:35:11 -07:00
Alex Forencich
5fa36eeaa7 Rework endpoints, update testbenches 2016-09-12 13:38:34 -07:00
Alex Forencich
06bfa1944c Add AXI stream switch module, generator script, and testbench 2016-07-25 13:12:10 -07:00