FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-02-04 07:13:13 +08:00
Code Issues Projects Releases Wiki Activity
841 Commits 1 Branch 0 Tags
Commit Graph

3 Commits

Author SHA1 Message Date
Alex Forencich
a3f6e36777 Use release version of cocotb for CI 2021-03-17 19:41:07 -07:00
Alex Forencich
4a98858bea Forward arguments to pytest 2020-12-28 20:19:46 -08:00
Alex Forencich
a894af4815 Add tox.ini 2020-12-28 01:12:08 -08:00