FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
08dd43defc Add frame length asserts to gigabit MAC testbench 2015-02-28 23:08:53 -08:00
Alex Forencich
6dee616834 Add gigabit MAC module 2015-02-26 19:16:08 -08:00