FPGA/verilog-ethernet
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10 Commits

Author SHA1 Message Date
sungsoo.han
edaec3bd38 add LAST_ENABLE to axis_arb_mux 2021-08-17 16:00:23 +09:00
Alex Forencich
4fa3870dea Remove string parameters 2021-06-02 15:08:43 -07:00
Alex Forencich
59a979aeda Add parameters to testbench 2018-12-09 00:05:38 -08:00
Alex Forencich
940c1210c1 Convert arbitrated mux to verilog parametrized arbitrated mux 2018-10-24 13:49:17 -07:00
Alex Forencich
5df7efe516 Happy new year 2018-02-26 12:25:20 -08:00
Alex Forencich
496c63bd1c Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream arbitrated mux 2017-11-20 20:15:08 -08:00
Alex Forencich
aebe0549dd Happy new year 2017-05-18 13:35:11 -07:00
Alex Forencich
5fa36eeaa7 Rework endpoints, update testbenches 2016-09-12 13:38:34 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
5f0d23a3ad Add AXI arbitrated mux module and testbench 2014-11-13 02:01:45 -08:00