FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
c5f44c70d1 Add parameter documentation 2019-07-24 13:54:21 -07:00
Alex Forencich
d2df971fc9 Add AXI stream frame length measurement module and testbenches 2019-03-07 22:57:46 -08:00