FPGA/verilog-ethernet
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250 Commits 1 Branch 0 Tags
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10 Commits

Author SHA1 Message Date
Alex Forencich
c5f44c70d1 Add parameter documentation 2019-07-24 13:54:21 -07:00
Alex Forencich
6c1ea89a66 Rename ports 2018-10-25 11:52:08 -07:00
Alex Forencich
5df7efe516 Happy new year 2018-02-26 12:25:20 -08:00
Alex Forencich
b0d7820f5b Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL FIFO 2017-11-20 21:32:46 -08:00
Alex Forencich
aebe0549dd Happy new year 2017-05-18 13:35:11 -07:00
Alex Forencich
f89620008d Remove reset dependence 2016-06-27 11:26:15 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
ac97cffc2b Properly reset all registers 2015-07-13 23:15:09 -07:00
Alex Forencich
dfab866e99 Remove unused reg 2015-07-13 23:09:02 -07:00
Alex Forencich
10fd51f192 Add SRL FIFO module and testbench 2014-12-03 18:49:33 -08:00