FPGA/verilog-ethernet
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308 Commits 1 Branch 0 Tags
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8 Commits

Author SHA1 Message Date
Alex Forencich
47ca9a8725 Replace eth_crc modules for generic lfsr module 2016-06-28 17:31:58 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
71235c0b92 64 bit Ethernet FCS checker optimizations 2015-11-03 15:32:23 -08:00
Alex Forencich
9d90f09de5 Rework CRC check 2015-10-09 22:56:52 -07:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
0be84e3b03 Write to _next instead of _reg in async block 2015-05-04 01:17:39 -07:00
Alex Forencich
db6a6e23f5 Add 64 bit Ethernet FCS checker 2015-03-22 01:05:57 -07:00