FPGA/verilog-ethernet
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308 Commits 1 Branch 0 Tags
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7 Commits

Author SHA1 Message Date
Alex Forencich
47ca9a8725 Replace eth_crc modules for generic lfsr module 2016-06-28 17:31:58 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
5a4b480c7e Update testbenches for python 3 2015-03-21 22:31:01 -07:00
Alex Forencich
8ba6cf00d6 Test very short packets 2015-03-04 12:58:22 -08:00
Alex Forencich
43999fb360 Add testbench for FCS insert with padding 2015-03-03 00:46:53 -08:00
Alex Forencich
ff14639eea Test FCS inserter with padding insertion enabled 2015-02-28 23:13:02 -08:00
Alex Forencich
bfe6c37ca9 Add ethernet FCS inserter and checker 2015-02-26 19:00:33 -08:00