FPGA/verilog-ethernet
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287 Commits

Author SHA1 Message Date
Alex Forencich
4a16c9070b Fix mixed assignments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 01:24:22 -07:00
Alex Forencich
85e4f1d8ba Add PHY RX status output for a more reliable link up indication 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:22:30 -07:00
Alex Forencich
a855fb3fb6 Use correct sync types 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:22:01 -07:00
Alex Forencich
e06eb07621 Set PTP CDC NS width to 6 in MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:20:42 -07:00
Alex Forencich
9012e25211 Fix PTP timestamp capture delay in axis_xgmii_tx_32 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:16:24 -07:00
Alex Forencich
7cb15647e7 Better handling of integrator saturation in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:15:31 -07:00
Alex Forencich
d96d5dfba0 Fix clock active detection in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:13:36 -07:00
Alex Forencich
7e5f6a2589 Remove extraneous code 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 18:54:29 -07:00
Alex Forencich
4676296c49 Add block names 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 18:51:27 -07:00
Alex Forencich
77617167fa Fix PTP TS FIFO instantiations 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 17:34:54 -07:00
Alex Forencich
0ad02db4a8 Fix PTP timestamp capture in axis_xgmii_rx_32 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 17:18:02 -07:00
Alex Forencich
af0e15b241 Fix MAC RX PTP timestamp in sideband for axis_baser_rx_64 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 17:14:41 -07:00
Alex Forencich
80a25731b8 Fix MAC RX PTP timestamp in sideband 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:58:47 -07:00
Alex Forencich
609aac39a0 Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:47:30 -07:00
Alex Forencich
9b5a8cf24a Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 17:39:44 -07:00
Alex Forencich
6f2d581d62 Add output pipeline to PTP clock CDC module 2022-03-27 23:47:14 -07:00
Alex Forencich
945f22fd33 Add output pipeline to PTP clock module 2022-03-27 23:46:49 -07:00
Alex Forencich
108c02d721 Simplify logic in PTP clock CDC module 2022-03-16 19:01:17 -07:00
Alex Forencich
0f2db26a8e Simplify logic in PTP clock module 2022-03-16 19:01:00 -07:00
Alex Forencich
7d8b5560b7 Fix backpressure bug 2021-12-31 22:58:38 -08:00
Alex Forencich
853c1737aa Simplify logic 2021-12-31 22:57:11 -08:00
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
786eabac4b Add missing wires 2021-10-20 02:01:33 -07:00
Alex Forencich
625c48c59c Add transceiver reset watchdog 2021-10-17 20:19:04 -07:00
Alex Forencich
7594ac0775 Init and reset to same value 2021-10-17 02:13:14 -07:00
Alex Forencich
9d4d8508ae Unconditionally pass through ordered set data to simplify decode logic 2021-10-16 01:25:48 -07:00
Alex Forencich
247aeae845 Detect bad XGMII encodings in PHY TX 2021-10-16 00:50:48 -07:00
Alex Forencich
3b2e6874d8 Rework XGMII to BASE-R encoder implementation 2021-10-16 00:48:01 -07:00
Alex Forencich
9667ef1f9c Detect sequence errors 2021-10-16 00:03:35 -07:00
Alex Forencich
5258bdc312 Improve bad block detection 2021-10-15 23:58:35 -07:00
Alex Forencich
571394f99f Translate LPI control characters 2021-10-15 23:53:53 -07:00
Alex Forencich
5494f3b678 Rewrite resets 2021-10-15 23:33:35 -07:00
Alex Forencich
c44e447db5 Transfer PTP information in tuser 2021-09-01 15:56:00 -07:00
Alex Forencich
e7de9b6ee6 Update PTP CDC instances 2021-08-26 01:07:56 -07:00
Alex Forencich
77938fa422 Update MAC modules for changes in FIFO modules 2021-08-26 00:55:12 -07:00
Alex Forencich
81673727a4 Fix broadcast address check 2021-08-08 13:25:39 -07:00
Alex Forencich
52d8867f73 Use BUFG instead of BUFIO2 for DDR input on Spartan 6 2021-07-31 12:45:38 -07:00
Alex Forencich
3edbe52bfa Use BUFG instead of BUFIO2 for DDR input on Spartan 6 2021-07-31 12:43:33 -07:00
Alex Forencich
5415c41c41 Remove string parameters 2021-06-02 17:50:26 -07:00
Alex Forencich
5e1329a992 Rework PHY bitslip timing 2021-05-05 00:35:43 -07:00
Alex Forencich
2796e681c9 Prevent latch inference 2021-03-30 22:23:40 -07:00
Alex Forencich
31c7349f90 Rewrite PTP clock CDC module for improved performance and timing closure at 25G 2021-03-30 15:57:46 -07:00
Alex Forencich
42950abf12 Refactor PTP period output, implement error output 2021-03-30 15:25:34 -07:00
Alex Forencich
1dd349399b PTP clock period is always positive 2021-03-17 21:13:36 -07:00
Alex Forencich
d1fc821c8b Fix simulation startup issue in rgmii_phy_if 2020-12-25 02:03:57 -08:00
Alex Forencich
909ccae151 Properly synchronize bad FCS status output 2020-12-01 14:01:15 -08:00
Alex Forencich
591527f5a7 Pass through FIFO pipeline parameters 2020-09-07 13:26:34 -07:00
Alex Forencich
839ea23ac4 Fix arb mux header backpressure 2020-05-17 21:50:24 -07:00
Alex Forencich
b31c390d3e Assume tkeep[0] always high 2020-05-05 16:17:51 -07:00
Alex Forencich
4d4c7df5b6 Parametrize eth_axis_fcs 2020-05-05 16:13:02 -07:00