FPGA/verilog-ethernet
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16 Commits 1 Branch 0 Tags
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11 Commits

Author SHA1 Message Date
Alex Forencich
4ad302949f Add defaults 2014-09-19 17:33:23 -07:00
Alex Forencich
fa72cc2035 Always make a copy of the data array 2014-09-19 17:32:27 -07:00
Alex Forencich
fdb31878e9 Remove length fields from ARP transmit module 2014-09-17 12:36:56 -07:00
Alex Forencich
33c044e035 Add invalid header and tuser assert checks and tests 2014-09-15 19:31:10 -07:00
Alex Forencich
85d11645eb Rename frame_error to error_header_early_termination 2014-09-15 19:08:01 -07:00
Alex Forencich
ea2b1b99d0 Add ARP frame to Ethernet frame modules 2014-09-15 19:06:02 -07:00
Alex Forencich
96f1e432f4 Remove old code 2014-09-15 19:02:41 -07:00
Alex Forencich
8e4d162667 Add ethernet frame to AXI stream modules 2014-09-14 01:06:48 -07:00
Alex Forencich
e1955a29da Add LocalLink to AXI stream bridge 2014-09-13 21:23:11 -07:00
Alex Forencich
74fa967071 Add AXI stream register 2014-09-13 21:22:06 -07:00
Alex Forencich
35f39a6f4b Add AXI stream FIFO 2014-09-13 21:21:39 -07:00