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Author	SHA1	Message	Date
Alex Forencich	4c711b8c7a	Update readme	2018-10-24 01:19:26 -07:00
Alex Forencich	fe0bf3b7c6	Remove old modules	2018-10-24 01:08:27 -07:00
Alex Forencich	00dc50826d	Update example designs	2018-10-24 01:03:44 -07:00
Alex Forencich	0aca4c7dcc	Update 10G MAC to use new modules	2018-10-24 00:54:41 -07:00
Alex Forencich	de69975872	Add AXI stream XGMII RX and TX modules and testbenches	2018-10-23 23:34:43 -07:00
Alex Forencich	030fe90bf5	Fix example design testbench	2018-10-19 15:33:25 -07:00
Alex Forencich	fbe698ebb7	Update Ethernet MAC testbenches	2018-10-19 15:31:47 -07:00
Alex Forencich	5e12f97518	MAC optimizations	2018-10-19 15:24:33 -07:00
Alex Forencich	14d8819cd3	merged changes in axis	2018-08-09 18:41:34 -07:00
Alex Forencich	8e5ec36ced	Optimize axis_arb_mux and improve latency	2018-08-09 18:40:50 -07:00
Alex Forencich	7a879aec1c	Remove extra registers	2018-08-09 18:38:41 -07:00
Alex Forencich	b5ec1c4a30	merged changes in axis	2018-08-09 11:24:21 -07:00
Alex Forencich	202fbcbb6f	Fix typo	2018-08-09 11:23:27 -07:00
Alex Forencich	2e9602b5b4	Update testbenches to use wait	2018-07-02 18:20:07 -07:00
Alex Forencich	65c64588a6	More endpoint updates	2018-07-02 16:33:13 -07:00
Alex Forencich	7775e7774d	merged changes in axis	2018-07-02 16:26:21 -07:00
Alex Forencich	ffc63e4b0d	Update readme	2018-07-02 16:25:29 -07:00
Alex Forencich	3063bba54b	Update testbenches to use wait	2018-07-02 16:19:35 -07:00
Alex Forencich	9390c3639b	More endpoint updates	2018-07-02 14:13:47 -07:00
Alex Forencich	63f9bbeced	Update endpoints	2018-07-02 13:20:49 -07:00
Alex Forencich	4cb51ac84e	merged changes in axis	2018-07-02 10:25:51 -07:00
Alex Forencich	268d011b89	Add wait method to sink	2018-06-30 00:21:26 -07:00
Alex Forencich	2ebffeb223	Be more pythonic	2018-06-30 00:21:02 -07:00
Alex Forencich	8982b4f4e1	Fix modsell pin	2018-06-29 13:00:41 -07:00
Alex Forencich	cd51821bf7	Add parameters	2018-06-22 18:56:05 -07:00
Alex Forencich	5b7646ccda	Rework ARP subsystem	2018-06-18 13:59:58 -07:00
Alex Forencich	25d1b373cc	Use don't care bits	2018-06-14 15:20:20 -07:00
Alex Forencich	6368529b6f	Add clock frequency annotation	2018-06-14 13:42:10 -07:00
Alex Forencich	e4672915e6	Update testbenches to use instances()	2018-06-13 22:43:11 -07:00
Alex Forencich	20486d438a	merged changes in axis	2018-06-13 22:36:26 -07:00
Alex Forencich	c5837daa2f	Update testbenches to use instances()	2018-06-13 22:26:10 -07:00
Alex Forencich	298ae4defa	Update MAC module instantiation	2018-06-13 22:16:02 -07:00
Alex Forencich	8e1f14e9a7	Add VCU118 10G example design	2018-06-13 19:30:07 -07:00
Alex Forencich	05c6743473	Update xdc	2018-06-13 19:18:59 -07:00
Alex Forencich	f4d7edf23f	Add VCU118 example design	2018-06-13 14:33:07 -07:00
Alex Forencich	415f723edc	Fix clock name	2018-06-11 16:37:34 -07:00
Alex Forencich	fea477db09	Add unused ports	2018-06-11 16:36:44 -07:00
Alex Forencich	3ae97c71a0	Add documentation	2018-06-04 18:21:55 -07:00
Alex Forencich	e95b39b36d	Update iddr/oddr Altera device support	2018-06-04 18:20:31 -07:00
Alex Forencich	c31757552b	Add crosspoint design	2018-05-31 16:27:56 -07:00
Alex Forencich	855b593ce5	Minor updates to 10G example designs	2018-05-31 16:05:41 -07:00
Alex Forencich	3e28af152a	Fix CI	2018-02-27 11:00:31 -08:00
Alex Forencich	6727e5a0bd	Happy new year	2018-02-27 01:47:56 -08:00
Alex Forencich	d0ef5f94a4	merge changes in axis	2018-02-27 01:46:35 -08:00
Alex Forencich	7c6da337b0	Happy new year	2018-02-27 01:39:25 -08:00
Alex Forencich	0fd157964a	Happy new year	2018-02-26 12:50:51 -08:00
Alex Forencich	0807a54c32	merged changes in axis	2018-02-26 12:45:29 -08:00
Alex Forencich	5df7efe516	Happy new year	2018-02-26 12:25:20 -08:00
Alex Forencich	3063a761e5	Support both versions of ML605	2018-02-26 00:18:14 -08:00
Alex Forencich	bd27156f35	AXI stream updates	2018-02-26 00:08:08 -08:00