FPGA/verilog-ethernet
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5 Commits

Author SHA1 Message Date
Alex Forencich
2a59c7db1c Update generate scripts to use argparse 2015-10-19 19:26:59 -07:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
af8bed8237 Update for compatibility with older versions of Python 2015-07-14 08:29:54 -07:00
Alex Forencich
2667c9c631 Update for compatibility with older version of Python 2015-07-09 11:35:55 -07:00
Alex Forencich
f6fcec08f3 Add IP mux module and testbench 2014-11-18 11:27:34 -08:00