FPGA/verilog-ethernet
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9 Commits

Author SHA1 Message Date
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
0f0ebfb87d Reorganize FIFO modules 2015-11-07 01:15:11 -08:00
Alex Forencich
382226ad59 Don't accept data until reset is complete 2015-10-08 23:46:59 -07:00
Alex Forencich
90ac361df5 Internal synchronous reset on async FIFOs 2015-10-08 13:03:42 -07:00
Alex Forencich
30a35c3d73 Convert async fifo to common reset 2015-10-08 12:52:51 -07:00
Alex Forencich
f387e4c300 Remove unused register 2015-07-09 11:13:12 -07:00
Alex Forencich
6bd7309b9d Properly reset all registers 2015-07-09 11:11:32 -07:00
Alex Forencich
51e65f5a22 Rework async FIFO resets and synchronization 2015-05-08 01:41:35 -07:00
Alex Forencich
918ef8f76c Add AXI async FIFO and testbench 2014-11-08 00:23:23 -08:00