FPGA/verilog-ethernet
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927 Commits 1 Branch 0 Tags
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10 Commits

Author SHA1 Message Date
Alex Forencich
5494f3b678 Rewrite resets 2021-10-15 23:33:35 -07:00
Alex Forencich
3684ccafb2 Make use of blocking statements consistent 2019-06-15 16:56:45 -07:00
Alex Forencich
296744b37e Make use of blocking statements consistent 2019-06-12 23:31:03 -07:00
Alex Forencich
6eff2f0030 Decouple transmit PTP tag enable and transmit PTP timestamp enable 2019-06-09 22:03:24 -07:00
Alex Forencich
2794c315e8 Fix synthesizer complaints 2019-06-08 17:36:09 -07:00
Alex Forencich
82fe5a6bdd Add PTP timestamp capture logic to MACs 2019-06-07 16:38:36 -07:00
Alex Forencich
659aa67481 Pack start packet strobes into the same signal 2019-06-06 17:13:14 -07:00
Alex Forencich
585ccefa15 Add TX underflow error signal 2019-03-26 12:42:08 -07:00
Alex Forencich
9891d75c2f Fix STATE_WAIT_END 2019-03-25 23:24:01 -07:00
Alex Forencich
ec38440d89 Add 10G Ethernet MAC/PHY combination modules and testbenches 2019-01-31 18:13:07 -08:00