FPGA/verilog-ethernet
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890 Commits 1 Branch 0 Tags
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11 Commits

Author SHA1 Message Date
Alex Forencich
4ac6d6803b Parametrize ARP components 2020-02-20 16:49:47 -08:00
Alex Forencich
1bec485766 Fix constants 2019-04-03 11:48:09 -07:00
Alex Forencich
d2fedc4134 Rename ports 2018-11-07 22:35:06 -08:00
Alex Forencich
5b7646ccda Rework ARP subsystem 2018-06-18 13:59:58 -07:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
96b6e7ca96 Ignore transient requests 2014-11-21 00:00:27 -08:00
Alex Forencich
2ae3581144 Add ARP module and testbench 2014-11-20 22:55:28 -08:00