FPGA/verilog-ethernet
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890 Commits 1 Branch 0 Tags
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5 Commits

Author SHA1 Message Date
Alex Forencich
52d8867f73 Use BUFG instead of BUFIO2 for DDR input on Spartan 6 2021-07-31 12:45:38 -07:00
Alex Forencich
edcfd0dc40 Prevent SRL inference in synchronizers 2019-03-28 12:36:32 -07:00
Alex Forencich
585ccefa15 Add TX underflow error signal 2019-03-26 12:42:08 -07:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
a3b5d5d167 Update RGMII PHY interface and add RGMII MAC wrappers 2017-05-31 18:40:49 -07:00