FPGA/verilog-ethernet
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110 Commits 1 Branch 0 Tags
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11 Commits

Author SHA1 Message Date
Alex Forencich
8cd0d3ee06 Update .travis.yml 2015-03-21 04:49:43 -07:00
Alex Forencich
eb9f7c13f1 Update .travis.yml 2015-03-21 04:47:21 -07:00
Alex Forencich
684f6967e5 Update .travis.yml 2015-03-21 04:40:57 -07:00
Alex Forencich
646ad2a293 Update .travis.yml 2015-03-21 04:39:27 -07:00
Alex Forencich
6bd28aa128 Update .travis.yml 2015-03-21 04:36:54 -07:00
Alex Forencich
d9c41d43f0 Update .travis.yml 2015-03-21 04:28:53 -07:00
Alex Forencich
d00471352f Update .travis.yml 2015-03-21 04:24:52 -07:00
Alex Forencich
30e597e3e0 Test with python 3 2015-03-21 03:32:42 -07:00
Alex Forencich
4981d7cacd Update MyHDL repo 2015-03-21 02:56:17 -07:00
Alex Forencich
385e358c08 Use non-broken myhdl 2014-12-03 18:02:53 -08:00
Alex Forencich
849f3c174a Add .travis.yml 2014-11-05 16:22:09 -08:00