FPGA/verilog-ethernet
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885 Commits 1 Branch 0 Tags
Commit Graph

249 Commits

Author SHA1 Message Date
Alex Forencich
5415c41c41 Remove string parameters 2021-06-02 17:50:26 -07:00
Alex Forencich
5e1329a992 Rework PHY bitslip timing 2021-05-05 00:35:43 -07:00
Alex Forencich
2796e681c9 Prevent latch inference 2021-03-30 22:23:40 -07:00
Alex Forencich
31c7349f90 Rewrite PTP clock CDC module for improved performance and timing closure at 25G 2021-03-30 15:57:46 -07:00
Alex Forencich
42950abf12 Refactor PTP period output, implement error output 2021-03-30 15:25:34 -07:00
Alex Forencich
1dd349399b PTP clock period is always positive 2021-03-17 21:13:36 -07:00
Alex Forencich
d1fc821c8b Fix simulation startup issue in rgmii_phy_if 2020-12-25 02:03:57 -08:00
Alex Forencich
909ccae151 Properly synchronize bad FCS status output 2020-12-01 14:01:15 -08:00
Alex Forencich
591527f5a7 Pass through FIFO pipeline parameters 2020-09-07 13:26:34 -07:00
Alex Forencich
839ea23ac4 Fix arb mux header backpressure 2020-05-17 21:50:24 -07:00
Alex Forencich
b31c390d3e Assume tkeep[0] always high 2020-05-05 16:17:51 -07:00
Alex Forencich
4d4c7df5b6 Parametrize eth_axis_fcs 2020-05-05 16:13:02 -07:00
Alex Forencich
8d909a082f Fix MAC FIFO parameters 2020-04-06 21:15:17 -07:00
Alex Forencich
1443c04ed3 Add missing reset 2020-02-23 17:18:59 -08:00
Alex Forencich
a55c354924 Parametrize Ethernet frame parsing 2020-02-21 21:37:57 -08:00
Alex Forencich
8618b24dea Force tkeep output high if KEEP_ENABLE is false 2020-02-21 14:30:13 -08:00
Alex Forencich
4ac6d6803b Parametrize ARP components 2020-02-20 16:49:47 -08:00
Alex Forencich
db56c938bf Replace generate with assign 2019-12-17 00:09:38 -08:00
Alex Forencich
e9c1c5a49d Fix state register width 2019-08-12 15:12:21 -07:00
Alex Forencich
e9949f57a9 Remove extraneous code 2019-08-05 13:27:12 -07:00
Alex Forencich
562e713837 Remove extraneous connections 2019-07-25 15:34:32 -07:00
Alex Forencich
ab77ac3858 Fix width 2019-07-19 18:16:07 -07:00
Alex Forencich
451db171d1 Don't leave output floating 2019-07-19 18:13:30 -07:00
Alex Forencich
16d1662d98 Add PTP timestamping infrastructure to 10G MACs 2019-07-18 23:13:46 -07:00
Alex Forencich
16755720d3 Add PTP tag inserter module 2019-07-18 22:39:50 -07:00
Alex Forencich
b26f923c2f Reset synchronizers 2019-07-18 18:35:30 -07:00
Alex Forencich
adb9c4d147 Fix initial values 2019-07-18 18:35:11 -07:00
Alex Forencich
3bd7be44fa Update FIFO instances and update MACs to use combined FIFO adapter module 2019-07-18 16:25:49 -07:00
Alex Forencich
4da1a83052 Constant FIFO depth 2019-07-17 23:36:10 -07:00
Alex Forencich
1279dcbf47 Back out previous change 2019-07-15 18:09:14 -07:00
Alex Forencich
cc1ff34f53 Add 64 bit timestamp support to ptp_clock_cdc 2019-07-15 16:36:02 -07:00
Alex Forencich
31cb54e67e Make old icarus verilog happy 2019-07-15 16:15:50 -07:00
Alex Forencich
9d553f2ad4 Also need to use tready 2019-07-15 15:24:12 -07:00
Alex Forencich
d88ada105d Add PTP TS extract module 2019-07-15 15:17:58 -07:00
Alex Forencich
77bae7a77e Add PTP clock CDC module and testbench 2019-07-15 15:16:17 -07:00
Alex Forencich
fdfb517761 Add PTP perout module and testbench 2019-06-27 01:30:18 -07:00
Alex Forencich
df04d7e68d CRC handling logic optimizations 2019-06-20 18:10:53 -07:00
Alex Forencich
9e7f4a9836 Remove unused state bit 2019-06-20 18:02:15 -07:00
Alex Forencich
eb1f38a749 More critical path optimizations 2019-06-19 15:06:55 -07:00
Alex Forencich
134ce04777 Add configurable serdes pipeline register chain 2019-06-19 00:57:28 -07:00
Alex Forencich
303dec8165 Sum errors across data and header 2019-06-19 00:25:41 -07:00
Alex Forencich
1d3554c37e Rework pointer handling to improve timing 2019-06-16 23:53:26 -07:00
Alex Forencich
7ec836baf6 IP header checksum optimizations 2019-06-16 22:01:11 -07:00
Alex Forencich
b17966f73d store_last_word timing optimization 2019-06-16 20:01:08 -07:00
Alex Forencich
55bf44117b shift_axis_extra_cycle timing optimization 2019-06-16 19:57:52 -07:00
Alex Forencich
3b959b2765 CRC handling logic optimizations 2019-06-16 17:39:28 -07:00
Alex Forencich
320a45c4ab Remove unused state bit 2019-06-16 17:33:14 -07:00
Alex Forencich
8bb243cd35 MAC termination detect timing optimizations 2019-06-16 15:44:41 -07:00
Alex Forencich
4f97303e44 Remove unused code 2019-06-16 15:38:35 -07:00
Alex Forencich
938479c246 MAC RX timing optimizations 2019-06-16 00:36:50 -07:00