FPGA/verilog-ethernet
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925 Commits 1 Branch 0 Tags
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10 Commits

Author SHA1 Message Date
Alex Forencich
6eff2f0030 Decouple transmit PTP tag enable and transmit PTP timestamp enable 2019-06-09 22:03:24 -07:00
Alex Forencich
82fe5a6bdd Add PTP timestamp capture logic to MACs 2019-06-07 16:38:36 -07:00
Alex Forencich
585ccefa15 Add TX underflow error signal 2019-03-26 12:42:08 -07:00
Alex Forencich
e644ce3895 Add start packet strobe timing outputs to MAC modules 2019-01-31 17:00:23 -08:00
Alex Forencich
0fd157964a Happy new year 2018-02-26 12:50:51 -08:00
Alex Forencich
8ff4312601 Update MAC modules to use new modules 2017-05-31 18:37:33 -07:00
Alex Forencich
9b2ac9dfc1 Happy new year 2017-05-18 13:47:45 -07:00
Alex Forencich
88150c9d5f Update and rework endpoints, update testbenches 2016-09-13 15:24:02 -07:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
6dee616834 Add gigabit MAC module 2015-02-26 19:16:08 -08:00