FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
5e1329a992 Rework PHY bitslip timing 2021-05-05 00:35:43 -07:00
Alex Forencich
591527f5a7 Pass through FIFO pipeline parameters 2020-09-07 13:26:34 -07:00
Alex Forencich
16d1662d98 Add PTP timestamping infrastructure to 10G MACs 2019-07-18 23:13:46 -07:00