FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
23fa1f1207 Handle tlast on first cycle 2015-03-03 21:46:02 -08:00
Alex Forencich
d3e30d0a73 Fix padding bug 2015-02-28 23:09:41 -08:00
Alex Forencich
bfe6c37ca9 Add ethernet FCS inserter and checker 2015-02-26 19:00:33 -08:00