FPGA/verilog-ethernet
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270 Commits 1 Branch 0 Tags
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5 Commits

Author SHA1 Message Date
Alex Forencich
af8bed8237 Update for compatibility with older versions of Python 2015-07-14 08:29:54 -07:00
Alex Forencich
2667c9c631 Update for compatibility with older version of Python 2015-07-09 11:35:55 -07:00
Alex Forencich
4d1180d74c Reverse priority in arbitrated mux 2014-11-16 02:20:44 -08:00
Alex Forencich
f1d075d974 Add enable signal 2014-11-16 02:13:43 -08:00
Alex Forencich
c90d5141ac Add ethernet arbitrated mux module and testbench 2014-11-14 22:11:49 -08:00