FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity
270 Commits 1 Branch 0 Tags
Commit Graph

8 Commits

Author SHA1 Message Date
Alex Forencich
51b5335318 Remove z from default states for FSM inference 2015-03-09 02:38:39 -07:00
Alex Forencich
0e26b3a8a4 Put back lane shifting logic 2014-10-28 00:54:15 -07:00
Alex Forencich
205be7ed27 Rework AXI ethernet modules to separate output register 2014-10-23 00:05:06 -07:00
Alex Forencich
d052bbb2bf Update 64-bit ethernet modules with lane shifting logic 2014-09-25 00:38:36 -07:00
Alex Forencich
4d012b4f52 Properly reset everything 2014-09-21 15:53:59 -07:00
Alex Forencich
d7f30a777b Update comments 2014-09-15 19:05:18 -07:00
Alex Forencich
46c29160ff Wait for header instead of payload 2014-09-15 19:03:31 -07:00
Alex Forencich
8e4d162667 Add ethernet frame to AXI stream modules 2014-09-14 01:06:48 -07:00