FPGA/verilog-ethernet
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245 Commits

Author SHA1 Message Date
Alex Forencich
16cd84123d Add user_sma_clk pins to VCU108 and VCU118 constraints files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-29 13:58:22 -08:00
Alex Forencich
3535e53746 Add example design for Alveo U55C and Alveo U55N/Varium C1100 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 15:40:14 -08:00
Alex Forencich
fe5f6aa3f5 Merge AU50 into Alveo example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 15:32:38 -08:00
Alex Forencich
de818ad621 Merge AU280 into Alveo example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 15:30:37 -08:00
Alex Forencich
58732ebeb3 Rework Alveo parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-10 15:25:38 -08:00
Alex Forencich
0986d1e901 Rework 7132 parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-08 13:36:21 -08:00
Alex Forencich
1b29a88b18 Rename AU200 to Alveo 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-08 11:50:50 -08:00
Alex Forencich
49513b45d4 Merge AU200, AU250, and VCU1525 designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-10-12 22:51:07 -07:00
Alex Forencich
e84da8dbfb Update HTG-9200 readmes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-26 23:12:52 -07:00
Alex Forencich
b5d1fadb7e Add makefiles for VU13P variant of HTG-9200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-26 15:07:16 -07:00
Alex Forencich
b316c6764e Use quad wrappers in ExaNIC X25 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:44:50 -07:00
Alex Forencich
f9eda00d68 Use quad wrappers in ExaNIC X10 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:43:29 -07:00
Alex Forencich
dc58b2447f Use quad wrappers in ZCU102 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:42:39 -07:00
Alex Forencich
d5df47d8b0 Use quad wrappers in ZCU106 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:42:04 -07:00
Alex Forencich
4618edcd8e Use quad wrappers in VCU108 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:15:29 -07:00
Alex Forencich
72de6c653a Use quad wrappers in AU50 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:09:00 -07:00
Alex Forencich
66987c8f62 Use quad wrappers in AU280 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:08:32 -07:00
Alex Forencich
22f327b35f Use quad wrappers in AU250 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:07:30 -07:00
Alex Forencich
65361d157b Use quad wrappers in AU200 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:06:28 -07:00
Alex Forencich
bd06e57764 Use quad wrappers in VCU1525 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:05:23 -07:00
Alex Forencich
c673ddbc14 Use quad wrappers in fb2CG@KU15P example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 00:37:44 -07:00
Alex Forencich
5d61059488 Use quad wrappers in ADM-PCIE-9V3 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 00:36:39 -07:00
Alex Forencich
68736d02ae Add 10G/25G design for Arista 7132LB-48Y4C switch 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 23:06:49 -07:00
Alex Forencich
351ec79fef Use quad wrappers in VCU118 example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 01:27:53 -07:00
Alex Forencich
75c2cc0acc Use quad wrappers in HTG9200 example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 01:24:26 -07:00
Alex Forencich
aaeeb05ac0 Fix PHY configuration connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 00:09:38 -07:00
Alex Forencich
fa05d4ff3c Add TX and RX enable inputs to MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-24 01:24:33 -07:00
Alex Forencich
20c542051d Use cfg prefix for configuration signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-22 17:14:52 -07:00
Alex Forencich
d6fc68947b Procedural generation of testbench drivers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-27 20:25:08 -07:00
Alex Forencich
78284572ef Remove XDC constraints that do not apply to Artix 7 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-23 18:35:22 -07:00
Alex Forencich
b1177eb4ed Rename HXT100G to HTG-640 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:17:26 -07:00
Alex Forencich
5d349c9cb2 Enable overtemp shutdown in constraints files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:17:12 -07:00
Alex Forencich
f4a8561652 Add HTG-9200 + HTG 6x QSFP28 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:16:59 -07:00
Alex Forencich
6bf727d3ef Add VCU118 + HTG 6x QSFP28 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 18:16:20 -07:00
Alex Forencich
31901754a6 Add FMC pins to VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:55:55 -07:00
Alex Forencich
19a76cbaf9 Add FMC pins to VCU108 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:55:44 -07:00
Alex Forencich
72a35c08ef Clean up FMC+ pins on HTG-9200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:55:19 -07:00
Alex Forencich
bdc974a60c Reorganize HTG-9200 PLL config 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:34:11 -07:00
Alex Forencich
efb3747967 Add IO delay false paths to HTG-9200 constraints file 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-20 21:15:20 -07:00
Alex Forencich
4a65e3594c Connect all PLL control lines on HTG-9200 board 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-20 01:17:49 -07:00
Alex Forencich
375b12865f Use QSFP Si570 for both QSFP modules on VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-19 17:00:33 -07:00
Alex Forencich
1be196279f Fix FIFO instances in S10DX example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 11:05:24 -07:00
Alex Forencich
50b6f53387 Update testbench clock frequencies 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-15 01:53:31 -07:00
Alex Forencich
d3fb11b2c3 Use unified 10G/25G design for HTG9200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 21:35:42 -07:00
Alex Forencich
412df8fea0 Use unified 10G/25G design for fb2CG@KU15P 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 21:34:53 -07:00
Alex Forencich
026a302c1c Use unified 10G/25G design for ExaNIC X25 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:45:47 -07:00
Alex Forencich
5dc38f11b7 Use unified 10G/25G design for Alveo VCU1525 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:42:40 -07:00
Alex Forencich
a221adc468 Use unified 10G/25G design for Alveo U50 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:40:38 -07:00
Alex Forencich
147435dfe1 Use unified 10G/25G design for Alveo U280 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:38:34 -07:00
Alex Forencich
ea80d853ed Use unified 10G/25G design for Alveo U250 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 19:53:21 -07:00