FPGA/verilog-ethernet
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5 Commits

Author SHA1 Message Date
Alex Forencich
5a4b480c7e Update testbenches for python 3 2015-03-21 22:31:01 -07:00
Alex Forencich
9265ab0946 Properly handle eth_fcs of None 2015-02-26 15:58:20 -08:00
Alex Forencich
f3ea7cd8ac Add FCS field to eth_ep 2015-02-24 20:26:24 -08:00
Alex Forencich
4ad302949f Add defaults 2014-09-19 17:33:23 -07:00
Alex Forencich
8e4d162667 Add ethernet frame to AXI stream modules 2014-09-14 01:06:48 -07:00