FPGA/verilog-ethernet
1
0
Fork 0
mirror of https://github.com/alexforencich/verilog-ethernet.git synced 2025-01-14 06:43:18 +08:00
Code Issues Projects Releases Wiki Activity
201 Commits 1 Branch 0 Tags
Commit Graph

4 Commits

Author SHA1 Message Date
Alex Forencich
5a4b480c7e Update testbenches for python 3 2015-03-21 22:31:01 -07:00
Alex Forencich
d73b296903 Properly handle short packets 2015-03-04 13:06:29 -08:00
Alex Forencich
218d3f1b0f Add assert for error_bad_fcs signal 2015-02-26 19:05:56 -08:00
Alex Forencich
bfe6c37ca9 Add ethernet FCS inserter and checker 2015-02-26 19:00:33 -08:00