FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
7594ac0775 Init and reset to same value 2021-10-17 02:13:14 -07:00
Alex Forencich
5494f3b678 Rewrite resets 2021-10-15 23:33:35 -07:00
Alex Forencich
dbbbc28059 Add 10G Ethernet PHY modules and testbenches 2019-01-16 18:00:56 -08:00