FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
5eb0d9f578 Move invert to top-level module 2016-01-25 13:21:35 -08:00
Alex Forencich
eb8dd775a1 Add 10G reference design for DE5-Net 2016-01-25 00:53:06 -08:00