FPGA/verilog-ethernet
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2 Commits

Author SHA1 Message Date
Alex Forencich
274831c268 Fix PTP clock CDC module timing constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-05 21:41:41 -07:00
Alex Forencich
7751aba8da Reorganize timing constraints 2021-05-18 16:15:41 -07:00