FPGA/verilog-ethernet
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5 Commits

Author SHA1 Message Date
Alex Forencich
1f80696b55 Use start_soon instead of fork 2021-12-10 18:19:11 -08:00
Alex Forencich
728e86c554 Update QSF/SDC files 2021-11-02 23:30:06 -07:00
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
e85deafca3 Update FIFO instance 2021-10-13 14:42:57 -07:00
Alex Forencich
cee82cb695 Add Stratix 10 DX 10G example design 2021-05-19 21:00:54 -07:00