FPGA/verilog-ethernet
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11 Commits

Author SHA1 Message Date
Alex Forencich
1f76eb4534 Update VCU108 XDC 2021-10-19 22:10:32 -07:00
Alex Forencich
c0c2dbce2a Update XDC files 2021-02-06 15:15:34 -08:00
Alex Forencich
9261f26f64 Update VCU108 XDC 2020-10-02 20:50:00 -07:00
Alex Forencich
b7c089dd22 XDC clean up 2020-07-13 23:58:30 -07:00
Alex Forencich
daf1d3106f Enable flash programming on VCU108 2019-06-26 01:28:54 -07:00
Alex Forencich
0ca8c9a59b Update example design timing constraints 2019-03-28 17:59:30 -07:00
Alex Forencich
cd6b87e984 Enable bitstream compression in example designs 2019-02-06 21:25:30 -08:00
Alex Forencich
415f723edc Fix clock name 2018-06-11 16:37:34 -07:00
Alex Forencich
3b47b422fa Fix Vivado clock groups 2016-10-06 17:52:23 -07:00
Alex Forencich
61d41789d7 Remove unused parameter; update XDC file 2016-07-13 11:57:14 -04:00
Alex Forencich
5afe1d7e1e Add example design for VCU108 board 2016-07-05 11:52:28 -04:00