FPGA/verilog-ethernet
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4 Commits

Author SHA1 Message Date
Alex Forencich
c5f44c70d1 Add parameter documentation 2019-07-24 13:54:21 -07:00
Alex Forencich
aa6991a4a5 Bitwise operators instead of generate 2018-12-09 00:03:09 -08:00
Alex Forencich
2bb9f11c9e Use logical operators 2018-10-24 22:24:27 -07:00
Alex Forencich
940c1210c1 Convert arbitrated mux to verilog parametrized arbitrated mux 2018-10-24 13:49:17 -07:00