68 Commits

Author	SHA1	Message	Date
Alex Forencich	e38ffe16b8	Adjust config vector assignment	2016-07-13 14:38:22 -04:00
Alex Forencich	018b3b2691	Fix signal width	2016-07-13 12:21:37 -04:00
Alex Forencich	61d41789d7	Remove unused parameter; update XDC file	2016-07-13 11:57:14 -04:00
Alex Forencich	5afe1d7e1e	Add example design for VCU108 board	2016-07-05 11:52:28 -04:00
Alex Forencich	1f52bf826d	Update vivado.mk	2016-07-05 11:17:16 -04:00
Alex Forencich	cbf1df718a	Add example design for Digilent Nexys Video board	2016-06-29 12:00:05 -07:00
Alex Forencich	b38c643384	Add more implementation parameters to gmii_phy_if	2016-06-28 19:35:52 -07:00
Alex Forencich	47ca9a8725	Replace eth_crc modules for generic lfsr module	2016-06-28 17:31:58 -07:00
Alex Forencich	b1dca3b57a	Add missing declaration	2016-02-12 18:27:54 -08:00
Alex Forencich	f36256c541	Add 10G reference design for HXT100G	2016-01-25 19:11:42 -08:00
Alex Forencich	5eb0d9f578	Move invert to top-level module	2016-01-25 13:21:35 -08:00
Alex Forencich	eb8dd775a1	Add 10G reference design for DE5-Net	2016-01-25 00:53:06 -08:00
Alex Forencich	c5b6202174	Update example design	2016-01-08 01:32:04 -08:00
Alex Forencich	6b23d83361	Set FIFO size in example design	2015-05-08 01:45:42 -07:00
Alex Forencich	6a012c992b	Update example design to use FIFO wrapper	2015-05-08 00:45:27 -07:00
Alex Forencich	5341987c45	Manage ethernet preamble properly	2015-04-01 19:44:25 -07:00
Alex Forencich	92830f87d8	Update for Python 3	2015-04-01 19:43:54 -07:00
Alex Forencich	d489468776	Add example design for Digilent Atlys board	2015-02-28 20:05:05 -08:00