17 Commits

Author	SHA1	Message	Date
Alex Forencich	0691c9d61b	Fix output pipeline issue	2016-09-02 10:43:21 -07:00
Alex Forencich	a961a9756a	Add FIFO output pipeline registers to aid block RAM output timing closure	2016-08-04 18:03:00 -07:00
Alex Forencich	b44e401b95	Update async FIFO resets	2016-07-27 13:42:44 -07:00
Alex Forencich	6fe4a033e5	Add dedicated pipeline registers for RAM addresses that are not reset	2016-06-27 12:25:18 -07:00
Alex Forencich	385c9cc90a	Fix Vivado block RAM inference	2016-06-27 12:10:36 -07:00
Alex Forencich	be4034071b	Happy new year	2016-01-05 00:24:20 -08:00
Alex Forencich	0f0ebfb87d	Reorganize FIFO modules	2015-11-07 01:15:11 -08:00
Alex Forencich	364b537312	Synchronize status signals for both clock domains in async frame FIFO	2015-10-09 15:14:54 -07:00
Alex Forencich	382226ad59	Don't accept data until reset is complete	2015-10-08 23:46:59 -07:00
Alex Forencich	90ac361df5	Internal synchronous reset on async FIFOs	2015-10-08 13:03:42 -07:00
Alex Forencich	30a35c3d73	Convert async fifo to common reset	2015-10-08 12:52:51 -07:00
Alex Forencich	e65173b7ee	Add overflow, bad_frame, and good_frame status outputs to frame FIFOs	2015-05-12 17:52:41 -07:00
Alex Forencich	51e65f5a22	Rework async FIFO resets and synchronization	2015-05-08 01:41:35 -07:00
Alex Forencich	9b7bad92f2	Reset pointers correctly	2015-04-19 17:51:27 -07:00
Alex Forencich	6e2eda256d	Improve frame drop logic in frame FIFOs, add DROP_WHEN_FULL option to disable input tready signal	2015-02-28 19:32:08 -08:00
Alex Forencich	698234c297	Update comments	2014-11-13 10:39:27 -08:00
Alex Forencich	10e0d7d1bb	Add AXI async frame fifo and testbench	2014-11-08 21:29:39 -08:00