FPGA/verilog-ethernet
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8 Commits

Author SHA1 Message Date
Alex Forencich
5fa36eeaa7 Rework endpoints, update testbenches 2016-09-12 13:38:34 -07:00
Alex Forencich
5fe35a79d2 Add tdest support to axis_ep 2016-07-25 11:28:35 -07:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
14f2d5e9f7 Add tkeep asserts to AXI stream EP 2015-05-03 00:23:58 -07:00
Alex Forencich
7b991bfe0e Update AXI stream endpoint to support multiple tdata signals 2015-03-21 03:35:42 -07:00
Alex Forencich
54bfdaa8c0 Cast WL to int 2015-03-21 03:19:43 -07:00
Alex Forencich
54bc201f52 Always make a copy of the data array 2014-09-19 17:32:27 -07:00
Alex Forencich
35f39a6f4b Add AXI stream FIFO 2014-09-13 21:21:39 -07:00