FPGA/verilog-ethernet
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6 Commits

Author SHA1 Message Date
Alex Forencich
74f32c6a59 Add missing PHY instance ports 2021-11-02 20:28:26 -07:00
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
21da6f58dc Rework GT instances in Alveo U280 design 2021-10-19 18:28:10 -07:00
Alex Forencich
fd908dd2aa Clean up clock connections 2020-08-06 17:15:38 -07:00
Alex Forencich
2570c75a0c Clean up AU280 design 2020-07-16 23:55:12 -07:00
Alex Forencich
f2f3c0f977 Add AU280 10G example design 2020-07-15 00:06:38 -07:00