FPGA/verilog-ethernet
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3 Commits

Author SHA1 Message Date
Alex Forencich
23fb9d0bd8 Remove deprecated assignments 2022-03-16 18:43:36 -07:00
Alex Forencich
1f80696b55 Use start_soon instead of fork 2021-12-10 18:19:11 -08:00
Alex Forencich
2d9f01f9fe Add cocotb testbenches for XGMII BASE-R encoder and decoder modules 2021-10-15 01:06:57 -07:00