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Author SHA1 Message Date
Alex Forencich
77938fa422 Update MAC modules for changes in FIFO modules 2021-08-26 00:55:12 -07:00
Alex Forencich
5273a8dda6 merged changes in axis 2021-08-26 00:14:22 -07:00
Alex Forencich
a613cc8a31 Fix alignment 2021-08-25 23:58:52 -07:00
Alex Forencich
6d70b0249e Update readme 2021-08-25 23:58:33 -07:00
Alex Forencich
6a030f5d5e Add axis_pipeline_fifo 2021-08-25 23:54:30 -07:00
Alex Forencich
92681fad8c Add DROP_OVERSIZE_FRAME parameter 2021-08-25 22:56:22 -07:00
Alex Forencich
0b2066abe3 Fix corner case with back-to-back single-cycle transfers 2021-08-25 19:19:30 -07:00
sungsoo.han
ceeea4b451 modify acknowledge assign 2021-08-17 16:42:26 +09:00
sungsoo.han
edaec3bd38 add LAST_ENABLE to axis_arb_mux 2021-08-17 16:00:23 +09:00
Alex Forencich
81673727a4 Fix broadcast address check 2021-08-08 13:25:39 -07:00
Alex Forencich
52d8867f73 Use BUFG instead of BUFIO2 for DDR input on Spartan 6 2021-07-31 12:45:38 -07:00
Alex Forencich
3edbe52bfa Use BUFG instead of BUFIO2 for DDR input on Spartan 6 2021-07-31 12:43:33 -07:00
Alex Forencich
29313d5e02 Add HTG-9200 10G example design 2021-07-08 11:58:04 -07:00
Alex Forencich
cf832f581c Set algorithm for pytest-split 2021-06-28 01:34:34 -07:00
Alex Forencich
97182ccf4e Update vivado.mk 2021-06-23 20:07:29 -07:00
Alex Forencich
763cc1669f Update test durations 2021-06-03 13:52:41 -07:00
Alex Forencich
5415c41c41 Remove string parameters 2021-06-02 17:50:26 -07:00
Alex Forencich
846183bc8b merged changes in axis 2021-06-02 17:06:26 -07:00
Alex Forencich
4fa3870dea Remove string parameters 2021-06-02 15:08:43 -07:00
Alex Forencich
0512664ae0 merged changes in axis 2021-06-01 13:03:13 -07:00
Alex Forencich
892ee84bff Delay command until write is acknowledged 2021-05-31 01:32:02 -07:00
Alex Forencich
3579310447 Clear active bit 2021-05-31 01:31:30 -07:00
Alex Forencich
e32f65f563 Update test durations 2021-05-30 12:39:49 -07:00
Alex Forencich
5d9c982cd4 Add switch testbenches 2021-05-30 12:33:29 -07:00
Alex Forencich
34d5a4fed5 Add wrapper generator for RAM switch 2021-05-30 12:32:26 -07:00
Alex Forencich
9417d5f749 Use cocotb.top 2021-05-30 12:32:02 -07:00
Alex Forencich
16b174b490 Print addressing configuration 2021-05-30 12:19:01 -07:00
Alex Forencich
e3183862bb tkeep always active inside RAM switch 2021-05-30 12:12:10 -07:00
Alex Forencich
56a3b8fe92 Fix indexed part select error in degenerate case when M_COUNT = 1 2021-05-30 12:11:46 -07:00
Alex Forencich
8e5c4874eb Fix switch wrapper parameters 2021-05-30 12:10:04 -07:00
Alex Forencich
c1bfa8cc41 Add tuser assert tests 2021-05-25 00:55:59 -07:00
Alex Forencich
a7905ed681 Add stress tests 2021-05-25 00:31:20 -07:00
Alex Forencich
a7ebfdcebb Add arbitration test 2021-05-25 00:13:32 -07:00
Alex Forencich
b09e01ba48 Update S10MX SDC 2021-05-19 21:57:48 -07:00
Alex Forencich
9df253aa59 Update readme 2021-05-19 21:57:33 -07:00
Alex Forencich
cee82cb695 Add Stratix 10 DX 10G example design 2021-05-19 21:00:54 -07:00
Alex Forencich
13c1bbe79a Update S10MX QSF 2021-05-19 16:48:58 -07:00
Alex Forencich
0c493c4ba1 Update readme 2021-05-18 22:11:32 -07:00
Alex Forencich
28686fb115 Update readme 2021-05-18 22:05:44 -07:00
Alex Forencich
20c7967715 Update readme 2021-05-18 19:16:48 -07:00
Alex Forencich
bf6fddd1db Add Stratix 10 MX 10G example design 2021-05-18 19:16:30 -07:00
Alex Forencich
40265a3e1c Add timing constraints for Quartus Prime Pro 2021-05-18 18:30:33 -07:00
Alex Forencich
7751aba8da Reorganize timing constraints 2021-05-18 16:15:41 -07:00
Alex Forencich
f236e7dff1 merged changes in axis 2021-05-18 16:03:37 -07:00
Alex Forencich
b7f3faa628 Add timing constraints for Quartus Prime Pro 2021-05-18 16:02:36 -07:00
Alex Forencich
e9f7723312 Reorganize timing constraints 2021-05-16 23:28:00 -07:00
Alex Forencich
5e1329a992 Rework PHY bitslip timing 2021-05-05 00:35:43 -07:00
Alex Forencich
c021d01c26 Update example design readmes 2021-05-04 15:48:12 -07:00
Alex Forencich
244f136ca7 Remove travis-ci 2021-04-03 17:09:12 -07:00
Alex Forencich
b56bc11598 Update readme 2021-04-03 17:00:18 -07:00