FPGA/verilog-ethernet
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5 Commits

Author SHA1 Message Date
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
f93310b85b Add GMIIFrame object and add tests and asserts for GMII error signal 2015-05-07 19:10:44 -07:00
Alex Forencich
5a4b480c7e Update testbenches for python 3 2015-03-21 22:31:01 -07:00
Alex Forencich
47a3a50b65 Move preamble out of gmii endpoint 2015-03-03 23:47:27 -08:00
Alex Forencich
bb31d57921 Add GMII endpoint module 2015-02-26 19:15:31 -08:00